1 document # sram100 rev or revised october 2005 features 16 x 4 static ram fast access time ? 35 ns commercial and industrial available in the following packages: ? 16-pin pdip inverted outputs description the P4C189 is a 64-bit high-speed static ram with a 16 x 4 organization. the memory requires no clocks or refreshing and has equal access and cycle times. inputs and outputs are fully ttl compatible. operation is from a single 5 volt supply. the output data is the complement P4C189 high speed 16 x 4 static cmos ram with inverting outputs functional block diagram pin configuration 5v power supply 10% for both commercial and industrial temperature ranges. separate i/o fully static operation with equal access and cycle times 3-state outputs for data bus applications of the written data. the P4C189 is offered in a 16-pin dip package. devices are offered in both commercial and industrial temperature ranges. dip (p7)
P4C189 page 2 of 8 document # sram100 rev or commercial symbol v oh v ol v ih v il i il i ih i sc parameter output high voltage output low voltage input high level input low level input low current input high current output short circuit current test conditions v cc = min., v in = v ih or v il , i oh = ?3.0 ma v cc = min., v in = v ih or v il , i ol = 24 ma v in = 0.5 v (except cs ) v cc = max, v in = 2.7v v cc = max., v out = 0.0v i l output leakage current industrial P4C189 min. 2.4 2.0 max. 0.5 0.8 -0.6 5 -60 55 70 unit v v v v ma a ma ma power supply current 50 a v cc = max. i cc v out = v cc , v cc = max. maximum ratings (1) symbol parameter value unit v cc power supply pin with ? 0.5 to +7 v respect to gnd terminal voltage with ? 0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ? 55 to +125 c symbol parameter conditions typ. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 7 pf capacitances (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) recommended operating conditions symbol parameter value unit t bias temperature under ? 55 to +125 c bias t stg storage temperature ? 65 to +150 c i out dc output current 20 ma grade (2) commercial industrial ambient temp 0c to 70c ?40c to 85c gnd 0v vcc 5.0v 10% 5.0v 10% 0v dc electrical characteristics over recommended operating temperature and supply voltage (2) v in = 0.5 v ( cs ) -1.2 -150 notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. ce is low and we is high for read cycle. 6. we is high, and address must be valid prior to or coincident with ce transition low. 7. transition is measured 200mv from steady state voltage prior to change with specified loading in figure 1. this parameter is sampled and not 100% tested. 8. read cycle time is measured from the last valid address to the first transitioning address.
P4C189 page 3 of 8 document # sram100 rev or addressed word is read out on the inverting outputs ( o 0 through o 3 ). the outputs of the memory go to an inactive high impedance state whenever chip select ( cs ) is high, or during the write operation when write enable ( we ) is low. an active low write enable ( we ) controls the writing/ reading operation of the memory. when chip select ( cs ) and write enable ( we ) are low, the information on data inputs (d 0 through d 3 ) is written into the addressed memory word. reading is performed with chip select ( cs ) low and write enable ( we ) high. the information stored in the functional description notes: h = high l = low x = don't care high z = implies outputs are disabled or off. this condition is defined as high impedance state. mode cs cs cs cs cs we we we we we output standby h x high z read l h d out write l l high z truth table timing waveform of read cycle no. 1 (5) sym. t rc t aa t ac t hz read cycle time chip enable access time output hold from address change chip enable to output in low z chip disable to output in high z -35 unit ns ns ns ns ns ns ac characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) min 35 2 2 max 35 15 10 parameter address access time t oh t lz
P4C189 page 4 of 8 document # sram100 rev or timing waveform of write cycle no. 1 ( we we we we we controlled) (9) sym. t wc t cw t aw t as t wp t ah t dw t dh t wz t ow parameter chip enable time to end of write address valid to end of write address set-up time write pulse width address hold time from end of write data valid to end of write data hold time write enable to output in high z output active from end of write ac characteristics?write cycle (v cc = 5v 10%, all temperature ranges) (2) -35 min 35 15 15 0 15 2 15 2 0 max 15 unit ns ns ns ns ns ns ns ns ns ns write cycle time timing waveform of read cycle no. 2 (6)
P4C189 page 5 of 8 document # sram100 rev or notes: 9. cs and we must be low for write cycle. 10. if cs goes high simultaneously with we high, the output remains in a high impedance state. timing waveform of write cycle no. 2 ( cs cs cs cs cs controlled) (9) 11. write cycle time is measured from the last valid address to the first transition address.
P4C189 page 6 of 8 document # sram100 rev or selection guide the P4C189 is available in the following temperature range, speed, and package options. ordering information speed (ns) 35 commercial temperature plastic dip -35pc industrial temperature plastic dip -35pi temperature range package
P4C189 page 7 of 8 document # sram100 rev or plastic dual in-line package pkg # # pins symbol min max a 0.145 0.200 a1 0.020 - b 0.014 0.023 b2 0.040 0.060 c 0.008 0.016 d 0.740 0.780 e1 0.240 0.260 e 0.300 0.320 e eb 0.310 0.365 l 0.125 0.150 0 15 0.100 bsc p7 16 (300 mil)
P4C189 page 8 of 8 document # sram100 rev or revisions document number : sram100 document title : P4C189 high speed 16 x 4 static cmos ram with inverting outputs rev. issue date orig. of change description of change or oct-05 jdb new data sheet
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